Switching element and method for controlling the same

ABSTRACT

The invention relates to a switching element and method for controlling the same, for high-speed data traffic. The switching element comprises two input ports (I1, I2) and two output ports (01, 02), wherethrough data is transmitted in parallel form as data elements; a switching unit (1) for connecting the input and output ports; and a control unit (2), by means of which, on the basis of the address part of each data element, the bus is connected through the switching unit in between the input and output port for sending data elements.

BACKGROUND OF THE INVENTION

The invention relates to the switching element for high-speed datatraffic.

The invention also relates to a method for controlling the said element.

The development of high-speed digital broadband networks and real-timemultimedia services based on these networks sets new demands on thehardware and software solutions in these systems. The data transfer ratefor instance in a MAN network (Metropolitan Area Network) is 140 Mbps,and in FDDIs (Fiber Distributed Data Interface) 100 Mbps. If packetrouting is performed in these environments, there is a demand of 100-600Mbps throughput of data between data transmission and processingcomponents.

As examples of hardware which demand high data flow rates and thus highdata throughput, let us mention high-speed packet switched networks(ATM), routing between FDDI, LAN and MAN networks, real-time digitalvideo compression, real-time multimedia coding (ASN. 1+VER), real-timesecurity algorithms and multiprocessor machines with distributedoperating systems (e.g. MACH-supercomputer).

High data throughput demands high data transfer rates between the inputand output of the system. In the prior art there are knowntransputer-type solutions where the processors are connected to eachother with 30 Mbps serial connections. However, these connections aredifficult to apply, because the fast data stream should be effectivelydistributed over the transputer network. This would demand some kind ofdistribution frontend in the system.

SUMMARY OF THE INVENTION

The object of the invention is to introduce a new switching element andmethod for controlling the same, by means of which element for instancehigh-speed broadband data networks can be realized, as well as real-timemultimedia services based on these networks. A general object of theinvention is to provide a versatile switching element to be applied inmany different environments, such as in microprocessor bus solutions forconnecting processors and memory units or other similar resources, aswell as in high-speed digital networks.

The switching element of the invention for high-speed data trafficcomprises two input ports and two output ports, through which data istransmitted in data elements, which consist of at least an address partand a data part; a switching unit for connecting the input and outputports; and a control unit whereby the bus is coupled, on the basis ofthe address part of each data element, through the switching unit, inbetween the input port and at least one output port for the transmissionof data. According to the invention, the input and output ports areports wherethrough data is transmitted in parallel form; the internalbuses of the switching element are parallel buses formed of an addressbus and a data bus, these buses being connected to the switching unit atthe input ports; the control unit comprises a decoding and coding unitof the address part of the data element, to which unit the input portsare connected by an address part bus; the switching unit is connected tothe output ports; and a clock signal channel is arranged in theswitching element, the said channel being connected to input buffers, tothe control unit and the switching unit; and by means of the clocksignal received through this channel, the transmission of data elements,performed through at least the first input port and the first outputport, is synchronized.

In a preferred embodiment of the invention, the second input port andthe second output port are provided with buffers, most advantageouslywith FIFO buffers. In that case a peripheral device or the like can becoupled to the second input port and to the second output portasynchronically, although the data elements are transmittedsynchronically through the switching element proper.

According to the invention, in the control method of the switchingelement, data elements are transmitted between input and output ports,so that when the data part of the data element fed in through the firstinput port carries data, it is sent, through the switching unit, eitherto the first or second output port or to both, depending on the addressof its address part.

According to the invention, the method includes the following steps:

a) when the data part of a data element fed in through the first inputport carries data, and it is sent, through the switching unit, to thesecond output port, the data element fed in through the second inputport is sent, through the switching unit, to the first output port, andif the data part of the data element fed in through the second inputport is empty, the empty data part or corresponding signal is sent tothe first output port;

b) when the data part of the data element fed in through the first inputport carries data and it is sent, through the switching unit, only tothe first output port, the data element fed in through the second inputport is sent, through the switching unit, to the second output port, andif the data part of the data element fed in through the second inputport is empty, this empty data part or corresponding signal is sent tothe second output port;

c) when the data part of the data element fed in through the first inputport carries data and is sent, through the switching element, to bothoutput ports, the supply of data through the second input port isprevented;

d) when the data part of the data element fed in through the first inputport is empty, the data element fed in through the second input port issent, through the switching unit, either to the first or second outputport or to both, depending on the address, and if the data part of thedata element fed in through the second input port is empty, this emptydata part is sent to the first output port; and

e) when the data element fed in through the second input port isentering both output ports, this data element can be sent to the firstoutput port of the switching element only in case the first input portsends a data element with an empty data part.

An advantage of the invention is that the switching element is simple instructure, data is transmitted in parallel form, and it has a highthroughput rate.

Another advantage of the invention is that the switching element is anall-round element which can be applied for instance in interconnectinghigh-speed microprocessors, memory circuits and I/O circuits, or it canbe used as a component in high-speed switching fields.

Another advantage of the invention is that the switching element caneasily be connected to other similar switching elements in order to formdifferent topologies.

Owing to the invention, the switching element can be realized as anintegrated circuit, or a large number of switching elements can beintegrated in one and the same component. It can also be integrated toform a part of a high-density circuit (VLSI).

BRIEF DESCRIPTION OF THE DRAWINGS

In the following the invention is explained in more detail withreference to the appended drawings, where

FIG. 1 is a block diagram of a switching element of the invention;

FIG. 2 illustrates a ring topology formed of the switching elements ofthe invention;

FIG. 3 illustrates a switching element of the invention, with thecontrol signals between the most important operational sectors;

FIG. 4 illustrates a parallel ring topology formed of the switchingelements of the invention; and

FIG. 5 illustrates a grid topology formed of the switching elements ofthe invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, the switching element of the invention comprises two inputports I1, I2 and two output ports O1, O2, a high-speed switching unit 1for interconnecting the input and output ports through internal buses 8,9, and a control unit 2. The input ports I1, I2 include input buffers 3,4. The output ports O1, O2 may also be provided with correspondingoutput buffers (not illustrated in FIG. 1).

Through the input ports I1, I2, the internal buses 8, 9, the switchingunit 1 and the output ports O1, O2, data is transferred in parallel formin a data element with a width of N bits, where N=an integral. It may befor instance 8, 16 or 32. The data element is formed of two parts: theaddress part with A bits, and the data part with D bits. In addition tothis, the data element may include additional bits, for instancecharacter check or priority bits. The ratio of the data element width tothe widths of the address and data parts is A+D=≦N.

Through the switching element, data elements are transmitted under thecontrol of the control unit 2. The control unit 2 includes an addressdecoding and coding unit, i.e. the address unit 2a, and the control unit2b proper. The address unit 2a is connected to the input buffers 3 and4. The control unit proper 2b is connected to the switching unit 1.Among the internal buses 8, 9 of the switching element, the address partbuses 8a, 9a are connected, apart from the swithching unit 1, also tothe address unit of the control unit. The data part buses 8b, 9b of theinternal buses 8, 9, are connected at the input buffers 3, 4 to theinputs of the switching unit. In the embodiment of FIG. 1, the switchingunit 1 is composed of two separate switching units 1a, 1b, the first 1aof which is connected to the first output port O1, and the second 1b tothe second output port O2.

Data can be transferred through the switching element of the inventionvia either of the input ports I1, I2, to both or one of the output portsO1, O2. Data transmission through the switching element is carried outsynchronically.

The switching element is provided with a clock signal channel 7, whichis connected to both input buffers 3, 4, to the control unit 2 and tothe switching unit 1, to its both parts 1a, 1b. By means of this clocksignal, the transfer of data elements through the switching element issynchronized.

The second input port I2, and the second output port O2 can be providedwith buffers, particularly FIFO buffers 5, 6 (FIFO=First In, First Out).The external connection to the second input port I2 and to the secondoutput port O2 can thus be either synchronous or asynchronous. The firstinput port I1 and the first output port O1 are in this case reserved forsynchronous data transfer. In FIG. 1, the FIFO buffers are representedwith dotted lines.

Through the switching element of the invention, data is transferred inparallel form as a data element with a width of N bits. The data elementis formed of an address part A and a data part D, as was maintainedabove. The data part may carry data, or it may be empty. An empty datapart is in this case indicated with a NULL address. The data part of thedata element is synchronously transferred through the switching element,by utilizing the address part of the data element and the addressinformation carried therein. The address information can be coded in maydifferent ways depending on the chosen topology, i.e. the method withwhich the group of switching elements is interconnected.

In the switching element of FIG. 1, data, i.e. data elements with Nbits, is transferred from either of the input ports to one or severaloutput ports. The input and output ports I1, I2 and O1, O2, are mutuallyarranged to operate in the following way.

When the data part of the data element fed in through the first inputport I1 carries data, it is sent, through the switching unit 1, eitherto the first O1 or second O2 output port, or to both depending on thecontents of the address part of the data element.

When the data part of the data element fed in through the first inputport I1 carries data and is sent, through the switching unit 1, to thesecond output port O2, then the data element fed in through the secondinput port I2 can be sent, through the switching unit 1, to the firstoutput port O1. If the data part of the data element fed in through thesecond input port is empty, this empty data part, or correspondingsignal, is sent to the first output port.

But if the data part of the data element fed in through the first inputport I1 carries data and is sent, through the switching unit 1, only tothe first output port O1, then the data element fed in through thesecond input port I2 is sent, through the switching unit 1, to thesecond output port O2. If the data part of the data element fed inthrough the second input port is empty, this empty data part orcorresponding signal is sent to the second output port.

If the data part of the data element fed in through the first input portcarries data and is sent, through the switching unit 1, to both outputports O1, O2, the feeding of data via the second input port I2 isprevented. In other words, through the second input port I2 data cannotbe fed into either of the output ports.

When the data part of the data element fed in through the first inputport I1 is empty, the data element fed in through the second input portI2 is sent, through the switching unit 1, depending on the respectiveaddress, either to the first 01 or second output port O2, or to both. Ifthe data part of the data element fed in through the second input portI2 is empty, this empty data part or corresponding signal is sent to thefirst output port O1.

If the data element fed in through the second input port I2 is going toboth output ports O1 and O2, this data element can be sent to the firstoutput port O1 only if the data element received through the first inputport I1 has an empty data part.

The hardware included in the switching element of the invention can berealized with known electronic components. The internal buses 8, 9 canalso be realized in many different ways. It is also obvious that theoperation of the switching element is controlled, through the controlunit 2, in a programmed fashion, which may at least partly be realizedby means of wiring and logic members.

The switching element of the invention can be realized as a VLSI unit oran independent circuit, whereby various switching topologies are formed.

FIG. 2 illustrates a ring topology, where the switching elements A ofthe invention are connected in a ring 12. This switching ring 12 isfurther connected to peripheral devices B. In this case the first outputport O1 of each switching element A is connected to the first input portI1 of the next switching element. Each peripheral device B is thenconnected to the switching element A by means of the second input portI2 and the second output port O2. Thus a number of the switchingelements of the invention are together connected to form a synchronousparallel ring with N bits. Several rings can be switched in successionthrough the switching elements A.

FIG. 3 illustrates a preferred embodiment of the switching element,particularly suited in ring-type topologies. This switching element isdescribed in a block diagram completed with the most important controlsignals between the operational sectors of the individual units.External connecting signals are also provided in the illustration.

The switching element of FIG. 3 comprises respective connections, i.e.the input and output ports I1, I2; O1, O2, and units as in the switchingelement of FIG. 1, and like numbers are used for like parts. Inconnection with the second input and output ports I2, O2, there areprovided the FIFO buffers 5, 6. In the output of the first switchingunit 1a, there is arranged an output buffer 10. In between the firstswitching unit 1b and the second buffer 6, there is also arranged anoutput buffer 11.

The switching element is connected to the ring through the input portsII: ADDR₋₋ IN₋₋ 1 and DATA₋₋ IN₋₋ 1, as well as through the output portsO1: ADDR₋₋ OUT₋₋ 1 and DATA₋₋ OUT₋₋ 1. Through the ports I2: ADDR₋₋ IN₋₋2 and DATA₋₋ IN₋₋ 2, as well as O2: ADDR OUT 2 and DATA₋₋ OUT₋₋ 2,peripheral devices are connected to the switching element. Theperipheral device can be, depending on the solution in question, forinstance a microcomputer, a memory card, a microprocessor, an I/O deviceor an interface to another ring.

The clock signal CLOCK is the timing signal of the ring, and it alsosynchronized the operation of the switching element. By using the FIFO₋₋FULL and FIFO₋₋ EMPTY signals, the switching element controls the datatransfer into the peripheral device. With the TRANS/EMPTY and LOOPsignals, the peripheral device informs the switching element to whichoutput port the data element stored in an output buffer must beconnected.

The NODE-ADDR signals are used for setting the address of the peripheraldevice, on the basis of which address the switching element knows whichdata elements coming from the ring the switching element must receiveand transfer further to the peripheral device.

The feeding of the address information of the peripheral device to theswitching element can also be performed through the FIFO memory. In thatcase, a separate control signal is needed to tell the control logic ofFIFO, that the registered data is the address of the peripheral device.The address is stored in a separate address buffer inside the switchingelement. This solution reduces the need of external connection signalsfor the switching element, because external address lines are notneeded.

The peripheral device connected to the switching element can requestpermission for transmission by using the TRANS₋₋ REQ signal. This signalis common to all peripheral devices connected to the ring, and severaldevices can request transmission simultaneously. Simultaneoustransmission requests can be priorized by adding priority information tothe address fields of empty data elements. On the bases of the priorityinformation, the switching element asking for transmission decideswhether or not the free interval is available for it. Anotherpossibility for solving the priority problem is to use severaltransmission request lines. Thus for instance peripheral devices with alower priority request transmission in a different line than those witha higher priority.

The TRANS₋₋ REQ signal is needed when the free intervals in the ring arecontinuously occupied, and the data sent by the peripheral device hasbeen waiting for transmission in the output buffer for several intervals(clock cycles). When the preset time has passed, the switching elementautomatically makes a transmission request to the TRANS₋₋ REQ line. Whenthose switching elements that continuously hold the free intervalsdetect that the transmission request line is activated, they releaseintervals, after a certain delay, for the disposal of other switchingelements. The duration of the delay depends on the arrangement inquestion and may vary in length, even with the switching elements of oneand the same ring. The length of the interval can be permanentlyprogrammed in the switching element, or it can be set from theperipheral device, through the FIFO memory.

When a peripheral device has obtained permission for transmission, theswitching element deletes the request from the TRANS₋₋ REQ line. Thisprocedure prevents any of the peripheral devices from obtaining all freeintervals in a busy situation. On the other hand, this procedure allowsa peripheral device with a large transmission capacity at best to obtainto whole capacity of the ring, at times when other peripheral devicesconnected to the ring do not request transmission. The allocation oftransmission turns is carried out rapidly, because the control decisionis made in the switching element. This arrangement enables real-timeprocessing with very high data transfer rates in the switching elements.

For the observation and control of the ring, the switching element canbe provided with a traffic-supervising logic in connection with theTRANS₋₋ REQ line. If a switching element has activated the TRANS₋₋ REQline but has not received permission for transmission for a long time,it can, after a predetermined period, start, under the control of thesupervising logic, removing from the ring such data elements that arenot addressed there. This procedure prevents the ring from being blockedin a situation where one of the peripheral devices or switching elementsis defective and has started sending irrational messages in all freeintervals.

A defective peripheral device can be identified for instance so that theswitching element (and/of peripheral device) that has detected thedefect sends an enquiry to all peripheral devices connected to the ring.Those peripheral devices that do not reply to this enquiry can beconsidered defective. A defective peripheral device can be separatedfrom the ring for instance by sending, via the ring, a command for therespective switching element connected to the defective device, thiscommand setting the said peripheral device in a state where theswitching element sends all data elements received from the ringdirectly to the output port of the ring. This is possible only when theswitching element itself is not defective.

The processing of the data received by the switching element from thering (port I1 ADDR₋₋ IN₋₋ 1 and DATA₋₋ IN₋₋ 1) is carried out on thebasis of the address part of the data elements. The switching elementexamines the address part in the address decoding and coding unit 2b(ADDRESS DECODING) and decides, on the basis of the coding result, wherethe received data element is connected by means of the control unit 2aproper. The processing and conducting to the right output buffer of thedata received from a peripheral device (port I2; ADDR₋₋ IN₋₋ 2 andDATA_(--IN) ₋₋ 2) is carried out by means of the LOOP and TRANS/EMPTYsignals, which are received in the control unit 2a.

If the address information of the peripheral device and the delayinformation needed for the transmission request and release of intervalsis sent through the FIFO memory 5, one or more additional signals arerequired for controlling the data coming from the peripheral device. Theprocessing of the data elements coming from the ring and a peripheraldevice is priorized, so that the data element coming from the ring has ahigher priority in cases where data is simultaneously going to the sameoutput port from both input ports.

The data elements proceeding in the ring can be divided into fivedifferent types with respect to the switching element. The following isa list of the data element types and a description of the measurescarried out by the switching element.

1) The received data element is addressed to the switching element

The switching element identifies in the address decoding and coding unit2b (ADDRESS DECODING), that the received data element is addressed to aperipheral device connected to the switching element. The RECEIVE signalis activated, and under the control of the control unit 2a proper(CONTROL AND TIMING) the received data element is stored in the inputbuffer 6 of the peripheral device. The writing of data in the inputbuffer further makes the FIFO₋₋ EMPTY signal inactive, thus informingthe peripheral device that the input buffer contains data ready forprocessing.

If a peripheral device has data ready for transmission, and the data iswaiting in the output buffer 5, the outgoing data element is connectedto the output port O1 of the ring at the same moment when the receiveddata element is stored in the input buffer. If the LOOP signal isactive, i.e. the data element contained in the output buffer must beswitched back to the peripheral device (data looping), the data elementis not transmitted.

2) The received data element is of the broadcast type

In the address decoding and coding unit 2b (ADDRESS DECODING), theswitching element identifies the received data element to be of thebroadcast type and activates the BROADCAST control signal. Under thecontrol of the control unit 2a (CONTROL AND TIMING) proper, the receiveddata element is simultaneously switched both to the input buffer 6 ofthe peripheral device and to the output port O1 of the ring. If theperipheral device contains data to be transmitted at the same time, thetransmission of data is prevented for the duration of this interval.

3) The received data element is empty

In the address decoding and coding unit 2b (ADDRESS DECODING), theswitching element identifies the received data element to be empty andactivates the EMPTY signal. If the peripheral device carries data to betransmitted (the TRANS/EMPTY signal is active), it is switched to theoutput port O1 of the outgoing data ring. If the LOOP signal is activeat the same time, the data element contained in the output buffer issimultaneously switched to the input buffer 6 of the peripheral device.If only the LOOP signal is active, the data element contained in theoutput buffer is switched to the input buffer of the peripheral device,and the empty data element received from the ring is switched to theoutput port of the ring. If the peripheral device does not contain anydata to be transmitted, an empty data element is switched to the outputport of the ring. In this case nothing is switched to the input bufferof the peripheral device.

4) The received data element is sent by the switching element itself

In the address decoding and coding unit 2b (ADDRESS DECODING), theswitching element identifies the received data element to have been sentby itself, and activates the DELETE signal. The switching elementremoves the received data element from the ring and destroys it. If theperipheral device simultaneously contains data to be transmitted (theTRANS/EMPTY signal is active, the LOOP signal inactive), the outgoingdata element is switched to the output port of the ring. If the LOOPsignal is active at the same time, the data element contained in theoutput buffer is simultaneously switched to the input buffer of theperipheral device. If only the LOOP signal is active, the data elementcontained in the output buffer is switched to the input buffer of theperipheral device, and an empty data element is switched to the outputport of the ring. If the peripheral device does not contain data to betransmitted, an empty data element is switched to the output port of thering. In this case nothing is switched to the input buffer of theperipheral device.

A data element is removed from the ring for instance in cases where theswitching element has sent a broadcast-type data element to the ring.After this data element has circulated in the ring, the switchingelement that sent it must remove the data element from the ring in orderto prevent the ring from being blocked. Another situation where aswitching element may receive a data element sent by itself is a defectcase, where the switching element addressed as the recipient of the dataelement is defective. If the switching element that sent the dataelement does not remove it from the ring, it remains to load the ringforever.

5) The address of the received data element is not identified

The address decoding and coding unit 2b (ADDRESS DECODING) of theswitching element does not identify the address of the received dataelement. The received data element is switched directly through theinput port of the ring to the output port thereof. If a peripheraldevice contains data to be transmitted, it is not switched during thisperiod. If the output buffer of the peripheral device contains data, andonly the LOOP signal is active, the data element is switched to theinput buffer of the peripheral device. If the peripheral device does notcontain data to be transmitted, the only control step carried out in theswitching element is to switch the data element coming from the ringback to the ring.

In FIG. 4, switching elements A of the invention are interconnected insimilar fashion as in FIG. 2. In this case two rings C and D, containinga number of switching elements, are parallelly coupled to each other byintermediation of peripheral devices B.

In FIG. 5, the switching elements A of the invention are coupled in agrid topology. In this case the number of parallel switching elements isfive, and five of them are likewise coupled in series. The system isalso provided with separate input and output buffers E, F, which arecontrolled by means of a separate control logic G.

The invention is not limited to the above described embodiments, butmany modifications are possible within the scope of the inventional ideadefined in the appended patent claims.

We claim:
 1. A method for controlling a switching element, comprisingthe steps of:a) feeding a data element between a plurality of inputports and output ports upon detecting that an address part of the dataelement corresponds to a predetermined address of the switching element,the input ports having at least a first and a second input ports, theoutput ports having at least a first and a second output ports, whereinwhen a data part of the data element fed in through the first input portcarries data, and the data part is sent, through a switching unit, tothe second output port, the data element fed in through the second inputport is sent, through the switching unit, to the first output port, andif the data part of the data element fed in through the second inputport is empty, either said empty data part or a corresponding signal issent to the first output port; b) feeding the data element between theinput ports and output ports detecting that the address part of the dataelement corresponds to the predetermined address of the switchingelement, wherein when the data part of the data element fed in throughthe first input port carries data and is sent, through the switchingunit, to the first output port only, the data element fed in through thesecond input port is sent, through the switching unit, to the secondoutput port, and if the data part of the data element sent in throughthe second input port is empty, either the empty data part or acorresponding signal is sent to the second output port; c) feeding thedata element between the input ports and output ports detecting that theaddress part of the data element corresponds to the predeterminedaddress of the switching element, wherein when the data part of the dataelement fed in through the first input port carries data and is sent,through the switching unit, to both first and second output ports, datafeeding through the second input port is prevented; d) feeding the dataelement between the input ports and output ports detecting that theaddress part of the data element corresponds to the predeterminedaddress of the switching element, wherein when the data part of the dataelement fed in through the first input port is empty, the data elementfed in through the second input port is sent, through the switchingunit, depending on the predetermined address, either to the first orsecond output port, or to both first and second output ports, and if thedata part of the data element fed in through the second input port isempty, the empty data part is sent to the first output port; and e)feeding the data element between the input ports and output portsdetecting that the address part of the data element corresponds to thepredetermined address of the switching element, wherein when the dataelement fed in through the second input port is going to bath first andsecond output ports, the data element is sent to the first output portof the switching element only in cases where the first input port sendsa data element with an empty data part.